The present invention relates generally to integrated circuit devices, and, more particularly, to an apparatus and method for implementing dynamic control of double gate devices.
Complementary metal-oxide-semiconductor (CMOS) technology is the predominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Performance enhancement between generations of devices is generally achieved by reducing the size of the device, resulting in an enhancement in device speed. This is generally referred to as device “scaling.” As conventional MOSFETs are scaled to channel lengths below 100 nm, certain problems arise. In particular, interactions between the source and drain of the MOSFET degrade the ability of the gate to control whether the device is on or off. This phenomenon is also referred to as a “short channel effect.”
Silicon-on-insulator (SOI) MOSFETs are formed with an insulator (typically, but not limited to, silicon dioxide) below the device active region, as opposed to conventional bulk MOSFETs, which are formed directly on silicon substrates, and hence have silicon below the active region. SOI is advantageous in one respect since it reduces unwanted coupling between the source and the drain of the MOSFET through the region below the channel. However, as device size is scaled even further, this approach also becomes increasingly difficult, since the distance between the source and drain is further reduced, leading to reduced gate control and increased short channel effects.
More recently, double gate devices have emerged as an alternative to conventional single gate CMOS devices for substantially increasing device performance. One specific type of double gate device is what is referred to as a “FinFET,” which includes a channel formed in a vertical fin that is controlled by a self-aligned double gate. The fin may be made thin enough such that the two gates can together control the entire fully depleted channel. Although it is a double gate structure, the FinFET is similar to existing planar MOSFET with respect to layout and fabrication techniques. Thus, a FinFET provides a range of channel lengths, CMOS compatibility, and large packing density compared to other double gate structures.
Notwithstanding the advantages of such newer types of device structures, power consumption still remains as one of the limiting factors in the overall chip design. For example, the scaling down of threshold voltage and gate oxide thickness results in a rapid increase in the amount of standby (leakage) power consumed. However, the critical dimensions of the devices fabrication processes have scaled faster than the ability to control parameters such as static power consumption. Accordingly, the constant search for new device structures, coupled with the difficulty in controlling device parameters, has resulted in significant variations across a semiconductor device. This variability in turn makes it more difficult to verify the power consumption, timing and functionality of a design before it can be implemented and manufactured.
In the case of single gate structures, threshold voltage control has been proposed through back-gate biasing to achieve high circuit performance during active periods, and low leakage current during idle periods by means of an extra gate. This technique also provides control through the back-gate body biasing to make devices more robust against design variations. In addition, it is well known that the threshold voltage of a single gate, SOI transistor threshold voltage may be dynamically changed by applying a voltage to a backgate located below the BOX (buried oxide) layer. However, there is presently no known method or structure for dynamically altering the threshold voltage of a double gate device such as a FinFET transistor.
In a FinFET, the first and second gates may be operated independently with respect to one other. Thus, one gate could be used for the control signal while the other gate is used to adjust the threshold voltage. In this case, however, the FinFET is essentially operating in a single gate mode with a backgate attached thereto. The problem therefore lies in configuring a device that may be maintained in the double gate mode of operation (i.e., the first and second gates connected to each other) when maximum device speed is desired, but that also has the capability of having its threshold voltage adjusted when low power operation and mitigation of design variations are desired.